Crystal driver circuit configurable for daisy chaining

ABSTRACT

A crystal driver integrated circuit configurable for daisy chaining including an amplifier core, an input pin and an output pin, and a controller that operates the amplifier core in any one of multiple operating modes. The operating modes include an oscillator mode for driving an external crystal coupled between the input and output pins to generate an oscillation signal at a target frequency, and an amplifier mode that amplifies an external oscillating signal provided to the input pin to provide an amplified oscillation signal on the output pin. The amplifier core includes a controllable current source that provides a core bias current to an amplifier having a level that is adjusted depending upon the operating mode and desired amplitude. The operating modes may include a bypass mode in which the amplifier core is disabled. The amplifier may be implemented as either an PMOS amplifier or an NMOS amplifier.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of U.S. Provisional Application Ser.No. 62/527,461, filed on Jun. 30, 2017, which is hereby incorporated byreference in its entirety for all intents and purposes.

This application is related to the following U.S. Patent Applicationswhich are hereby incorporated by reference in their entireties for allintents and purposes.

SERIAL FILING NUMBER DATE TITLE 15/639,038 Jun. 30, 2017 CRYSTALAMPLIFIER WITH ADDITIONAL HIGH GAIN AMPLIFIER CORE TO OPTIMIZE STARTUPOPERATION 15/639,137 Jun. 30, 2017 CRYSTAL AMPLIFIER WITH RESISTIVE DE-GENERATION 15/639,267 Jun. 30, 2017 CRYSTAL DRIVER CIR- CUIT WITH COREAM- PLIFIER HAVING UNBALANCED TUNE CAPACITORS 62/527,475 Jun. 30, 2017CRYSTAL DRIVER CIR- CUIT WITH EXTERNAL OSCILLATION SIGNAL AMPLITUDECONTROL

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates in general to crystal oscillators, andmore particularly, to a crystal driver circuit that is configurable intomultiple operating modes including an amplifier mode that may be usedfor daisy chaining.

Description of the Related Art

A crystal oscillator uses the mechanical resonance of a crystal tocreate an electrical sinusoidal signal having a precise frequency. Thecrystal oscillator includes a crystal amplifier providing a “negative”resistance that cancels losses of the crystal to establish and maintainoscillation. In certain configurations, the crystal amplifier mayinclude an N-channel MOS (NMOS) or a complementary MOS (CMOS) amplifierhaving an input and output for coupling across the crystal. The crystalmay be modeled as a series combination of a motional capacitance,inductance, and resistance, and the crystal amplifier may be modeled asa negative resistance.

In many electronic system configurations, multiple semiconductor chipsor integrated circuits may need an accurate clock signal. A crystaloscillator may incorporate a squaring buffer to convert a sinusoidaloscillation signal into a digital clock signal, but delivery of thedigital clock signal is problematic because of potential undesiredemissions and/or harmonics generated by square-wave type clock signals.Each integrated circuit may incorporate its own crystal amplifier thatmay be used to drive an external crystal, but this requires multiplecrystals.

SUMMARY OF THE INVENTION

A crystal driver integrated circuit configurable for daisy chainingaccording to one embodiment includes an amplifier core, an input pin andan output pin, and a controller that operates the amplifier core in anyone of multiple operating modes based on a mode input. The operatingmodes include an oscillator mode for driving an external crystal coupledbetween the input and output pins to generate an oscillation signal at atarget frequency, and an amplifier mode that amplifies an externaloscillating signal provided to the input pin to provide an amplifiedoscillation signal on the output pin. The amplifier core includes acontrollable current source that provides a core bias current to anamplifier, in which the level of the core bias current is adjusteddepending upon the operating mode. The operating modes may include abypass mode in which the amplifier core is disabled. The amplifier maybe implemented as either an PMOS amplifier or an NMOS amplifier.

The controller may adjust the current source to provide the core biascurrent so that the oscillation signal on the input pin has a firsttarget amplitude during the oscillator mode, or may adjust the currentsource to provide the core bias current so that the amplifiedoscillation signal on the output pin has a second target amplitudeduring the amplifier mode. The first and second target amplitudes may beequal.

The controller may disable a first tune capacitor coupled to theamplifier output node and may disable a second tune capacitor coupled tothe amplifier input node during the amplifier mode. The controller maydisable the tune capacitor coupled to the amplifier input node duringthe bypass mode. The crystal driver integrated circuit may include amemory, in which the controller may use a first stored value to adjustthe current source to set the core bias current during the oscillatormode, and may use a stored second value to adjust the current source toset the core bias current during the amplifier mode.

The crystal driver integrated circuit may include a select circuit and alevel detector. The select circuit has an output that conveys a selectedone of the amplifier input node and the amplifier output node based on aselect input. The level detector has an input coupled to the output ofthe select circuit and has an output providing a level value to thecontroller. The controller controls the select input of the selectcircuit to select the amplifier input node to set a level of the corebias current for the oscillator mode, and controls the select input ofthe select circuit to select the amplifier output node to set a level ofthe core bias current for the amplifier mode.

A crystal driver daisy chain configuration according to one embodimentincludes multiple crystal driver integrated circuits coupled in a daisychain configuration, in which at least one crystal driver integratedcircuit is operated in the amplifier mode having an output pin providingan amplified oscillation signal to an input pin of at least one othercrystal driver integrated circuit. The crystal driver daisy chain mayinclude a crystal oscillator providing an oscillation signal to an inputpin of one of the crystal driver integrated circuits operated in theamplifier mode. The crystal oscillator may be a first crystal driverintegrated circuit operated in the oscillator mode having an input pinproviding the oscillation signal.

Each of the crystal driver integrated circuits in the daisy chainconfiguration may be operated in the amplifier mode, including a firstreceiving an external oscillation signal at its input and providing afirst amplified signal at its output, and a last receiving a lastamplified oscillation signal. Intermediate crystal driver integratedcircuits may be included, each receiving an amplified oscillation signalat its input and providing an amplified oscillation signal at itsoutput. One or more crystal driver integrated circuits operated in thebypass mode may have its input pin coupled to receive an amplifiedoscillation signal from any of the crystal driver integrated circuitsoperated in the amplifier operating mode.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notlimited by the accompanying figures, in which like references indicatesimilar elements. Elements in the figures are illustrated for simplicityand clarity and have not necessarily been drawn to scale.

FIG. 1 is a simplified block diagram of an integrated circuit (IC)including a crystal oscillator (XO) system implemented according to oneembodiment of the present invention.

FIG. 2 is a simplified block diagram of the XO system of FIG. 1incorporating a single crystal amplifier and supporting circuitry.

FIG. 3 is a schematic and block diagram of the crystal amplifier of FIG.2 implemented according to one embodiment of the present invention showncoupled to a controller 216, and further including a select circuit, alevel detector, and a memory.

FIG. 4 is a schematic diagram of the amplifier of FIG. 3 according to aCMOS configuration.

FIG. 5 is a schematic diagram of amplifier of FIG. 3 according to anNMOS configuration.

FIG. 6 is a simplified schematic diagram of an adjustable tune capacitorthat may be used as either one or both of the tune capacitors of FIG. 3.

FIG. 7 is a simplified block diagram illustrating the IC of FIG. 1configured to operate in an oscillator mode including an externalcrystal, collectively forming a crystal oscillator.

FIG. 8 is a simplified block diagram illustrating the IC of FIG. 1configured to operate in a bypass mode.

FIG. 9 is a simplified block diagram illustrating the IC of FIG. 1configured to operate in an amplifier mode.

FIG. 10 is a simplified block diagram of a daisy chained configurationof a set of “N” ICs according to one embodiment of the presentinvention.

FIG. 11 is a simplified block diagram of a daisy chained configurationof a set of “N” ICs according to another embodiment of the presentinvention.

FIG. 12 is a simplified block diagram of a daisy chained configurationof a first set of “N” ICs and a second set of “P” ICs according toanother embodiment of the present invention.

FIG. 13 is a simplified block diagram of a daisy chained configurationof multiple sets of multiple ICs according to another embodiment of thepresent invention.

FIG. 14 is a simplified block diagram illustrating a first IC configuredto operate in the OSC mode, which provides an oscillation signal to theXI input pin of another IC configured in the AMP mode for use in any ofthe daisy chained configurations.

DETAILED DESCRIPTION

The inventor has recognized the need to share an oscillation signalamong multiple semiconductor chips or integrated circuits. He astherefore developed a crystal driver circuit that is configurable tooperate in an amplifier mode that may be used for daisy chainingmultiple integrated circuits. The crystal driver circuit includes acrystal amplifier with an amplifier input and an amplifier output whichmay be coupled across a crystal to form a crystal oscillator. In orderto facilitate sharing of an oscillation signal generated by anothercrystal amplifier or external oscillator, the crystal amplifier may beconfigured instead to operate in the amplifier mode providing anamplified oscillation signal to drive additional integrated circuits.Rather than connecting to a crystal, a crystal amplifier configured inthe amplifier mode amplifies an external oscillation signal received atits amplifier input and provides the amplified oscillation signal at itsoutput. The amplifier mode converts the crystal amplifier into a bufferthat may be used to drive additional integrated circuits with reduceddistortion. A level detector and controller may be included to adjust acore bias current of an amplifier core to ensure that the amplitude ofthe amplified oscillation signal is at a target level.

FIG. 1 is a simplified block diagram of an integrated circuit (IC) 100including a crystal oscillator (XO) system 102 implemented according toone embodiment of the present invention. The illustrated IC 100 is shownin simplified form including the XO system 102, which is provided togenerate a number “M” of clock signals, shown as CLK1, CLK2, . . . ,CLKM, in which M is any positive integer greater than 0. In oneembodiment, the IC 100 may incorporate only the XO system 102 as part ofa clock semiconductor chip or the like. Although the clock signalsCLK1-CLKM may be provided off chip via corresponding pins or interfacesor the like, these signals are digital clock signals in square-waveformat that may cause unwanted emissions and/or harmonics. Although notshown, the IC 100 may incorporate additional circuitry for implementingone or more desired electronic functions that may use one or more of theclock signals CLK1-CLKM, such as according to any of various wired orwireless communication applications. Wireless applications may include,for example, Bluetooth®, Zigbee, Wi-Fi, etc. Other functional circuitblocks and circuits may be included for particular applications, but arenot shown as not necessary for a full and complete understanding of thepresent invention. The IC 100 may be mounted on a printed circuit board(PCB) (not shown), a module (not shown), or the like as part of a largerelectronic system.

In one embodiment, the XO system 102 may be maintained in a power-downor standby mode when not being used. In the illustrated configuration,the IC 100 provides an activation signal ACT which is asserted toactivate or enable the XO system 102 and negated to place the XO system102 into a standby mode. The IC 100 also provides a MODE signal to theXO system 102 for placing the XO system 102 including any one ofmultiple operating modes as further described herein. The XO system 102may be coupled to an external device via an amplifier output pin XOand/or an amplifier input pin XI. As described further herein, forexample, MODE indicates an oscillator (OSC) mode, in which the XO system102 interfaces an external crystal 702 (FIG. 7) coupled between XI andXO. In the OSC mode, the XO system 102 develops an oscillating signalwith a target frequency and/or target amplitude. Alternatively, anexternal oscillator may provide an oscillation signal to XI, and MODEmay indicate an amplifier (AMP) mode. In the AMP mode, the externaloscillation signal is amplified by the XO system 102 and provided as anoutput oscillation signal on XO. MODE may further include a bypass (BYP)mode, in which the external oscillation signal may be directly used todevelop the clock signals CLK1-CLKM.

The electronic system incorporating the IC 100 may be implemented anyone of various configurations, such as a communication device(hand-held, mobile, stationary, etc.), a computer system (laptop,desktop, server system, etc.), a computer peripheral device (e.g.,printer, router, etc.), or any other devices that may be networkedtogether via wired and/or wireless communications. The presentdisclosure contemplates the use of the IC 100 incorporated within adevice that may be part of a suite of components of an Internet ofThings (IoT) platform or the like. The components or devices may bepowered from an external source (e.g., AC outlet or the like), or may bebattery-operated. Generally, it is understood that the present inventionmay be used in any application that uses a crystal oscillator.

FIG. 2 is a simplified block diagram of the XO system 102 incorporatinga single crystal amplifier 202 and supporting circuitry. XO isinternally coupled to an amplifier output node 204 and XI is internallycoupled to an amplifier input node 206. As used herein, “XO” generallyrefers to the XO pin and/or the amplifier output node 204 (unlessspecifically referencing the XO system 102), and “XI” generally refersto the XI pin and/or the amplifier input node 206. The crystal amplifier202 includes a tune capacitor (CTUNE) circuit 208 and an amplifier core210, which are both coupled to the amplifier input and output nodes 204and 206. The CTUNE circuit 208 includes a first capacitor C1 coupledbetween the amplifier output node 204 and a reference node and a secondcapacitor C2 coupled between the amplifier input node 206 and thereference node. The reference node develops a suitable positive,negative or zero voltage level, such as ground (GND). The capacitors C1and C2 are shown as adjustable capacitors, although fixed tunecapacitors are also contemplated. In an alternative embodiment, the tunecapacitors may be omitted and otherwise provided externally.

The amplifier input node 206, or XI, is coupled to an input of asquaring buffer 218, which converts an oscillating signal developed onXI, which generally has a sinusoidal waveform, to a squarewave clocksignal CK. CK is provided to an input of a level shifter 220, whichadjusts the voltage level of CK and provides a corresponding clocksignal CLK to an input of an inverting, selection, and buffering circuit222. The inverting, selection, and buffering circuit 222 incorporatesmultiple inverters, multiplexers (MUXes), and buffers or the like forproviding the clock signals CLK1-CLKM based on CLK, in which CLK1-CLKMmay include one or more inverted clock signals. The inverting,selection, and buffering circuit 222 may also convert one or more of theclock signals or inverted clock signals CLK1-CLKM from single-ended todifferential format. A controller 216 has corresponding outputs forselecting between each clock signal or its inverted version. One or moreof the selected clock signals may be provided directly to selectedportions of the IC 100. One or more of the selected clock signals mayalso be provided to other circuitry (not shown) for further processing,such as clock synthesizers or the like (not shown), for providing one ormore modified clock signals (e.g., changes of one or more of frequency,duty cycle, amplitude, etc.) for use by other portions of the IC 100.The particular clock signals or uses thereof are not further describedherein.

The controller 216 receives the ACT signal for activating the XO system102 and for returning the XO system 102 to the standby mode. Thecontroller 216 has an adjust output to adjust the capacitance values ofthe first and second adjustable capacitors C1 and C2 (when included andwhen adjustable). The controller 216 has one or more additional outputsfor adjusting operation of the amplifier core 210. The controller 216may also have one or more additional outputs for enabling various blocksand for controlling various parameters of the amplifier core 210.

The controller 218 also receives the MODE signal for controllingoperation of the crystal amplifier 202 according to a selected mode ofoperation as further described herein. The OSC mode is the normaloperating mode, in which the crystal amplifier 202 sustains oscillationof the external crystal 702 coupled between XI and XO by generating theappropriate level of negative resistance between XO and XI to develop anoscillation signal. The tune capacitors C1 and C2 collectively form atune capacitance CT for tuning the oscillating signal to a targetfrequency in the OSC mode.

In the AMP mode, the amplifier core 210 is instead used as an amplifierthat amplifies and/or buffers an external oscillation signal providedvia XI to provide an amplified oscillation signal on XO. The amplifiedoscillation signal may be used to provide an oscillation signal to oneor more external devices in a daisy chain configuration as furtherdescribed herein. In the AMP mode, the capacitance of C1 and C2 may beadjusted or otherwise disabled (e.g., set to zero capacitance). Forexample, if the external oscillation signal is provided from another ICsimilar to the IC 100 including an XO system similar to the XO system102, then C2 may be set to zero capacitance (although parasiticcapacitance may still be present on XI). Also, the capacitor C1 may beset, or otherwise adjusted, to control an amplitude of the oscillationsignal on XO. The amplitude at XO can also be controlled by the currentsupplied to the core, or by using both mechanisms together.Alternatively, the external oscillation signal may be provided by acapacitively coupled external clock source, in which case thecapacitance of C2 may be adjusted to control the amplitude of theexternal oscillation signal.

In the BYP mode, the crystal amplifier 202 is effectively shut off ordisabled and the external oscillation signal provided on XI is simplyprovided to the squaring buffer 218 for developing CLK1-CLKM. In the BYPmode, C2 may be disabled or have its capacitance set to zero.

FIG. 3 is a schematic and block diagram of the crystal amplifier 202implemented according to one embodiment of the present invention showncoupled to the controller 216, and further including a select circuit302, a level detector 304, and a memory 310. The select circuit 302 isshown as a multiplexer (MUX) or the like, having a pair of inputs forselecting between the XO and XI (i.e., between the amplifier output node204 and the amplifier input node 206) based on a select input receivinga select signal SEL from the controller 216. The select circuit 302provides a selected output to an input of the level detector 304. Thelevel detector 304 may be implemented as a peak detector, an amplitudedetector, a signal level detector, such as for determining theroot-mean-square (RMS) level of an input voltage level, etc. The leveldetector 304 provides a level detect value LD to an input of thecontroller 216. It is noted that the level detector 304 may incorporatethe select circuit 302 and receive SEL for selecting between XO or XI.In one embodiment, the level detector 304 asserts LD when a level of aselected one of the amplifier input and ouptut nodes XI or XO reaches alevel threshold. One or more threshold values TH1, TH2, etc., may bedefined. In one embodiment, the memory 310 is accessible by thecontroller 216 and may be provided to store at least one thresholdvalue, which is also accessible by the level detector 304 via a signalL_TH.

The amplifier core 210 includes an adjustable current source 306 and anamplifier 308. The current source 306 is coupled to a source voltageVDDA, and provides a core bias (CB) current to a source node 307developing a source voltage VS. The current source 306 includes anadjust input receiving a value CBA from the controller 216 for adjustingthe level of the core bias current. The current source 306 provides thecore bias current, CB, to the amplifier 308 referenced to GND. Theamplifier 308 is coupled to the amplifier output node 204 and theamplifier input node 206. C1 is coupled between XO and GND as previouslydescribed and receives an adjust signal CP1 from the controller 216.Similarly, C2 is coupled between XI and GND as previously described anreceives an adjust signal CP2 from the controller 216.

The controller 216 may be implemented as a digital state machine or thelike in which adjustments of the crystal amplifier 202 are made byproviding and/or updating changing digital code values to variouscomponents. Although the controller 216 is shown embodied within asingle block within the XO system 102, control functions may bedistributed at various locations within the XO system 102 and/or withinthe IC 100. One or more of the digital code values as described hereinmay be adjustable or otherwise programmable within a correspondingprogrammable memory or the like (not shown). CBA may be a digital codevalue provided to the current source 306, in which the controller 216adjusts CBA to adjust the core bias current provided to the source node307 accordingly. Likewise, the controller 216 may provide CP1 and CP2 asseparate digital control values for adjusting the capacitances of C1 andC2, respectively. The controller 216 may also provide enable signalsC1EN and C2EN used in conjunction with CP1 and CP2 to enable or disableone or both of the capacitors C1 and C2. The controller 216 may providetwo additional digital code values R1A and R2A, described further below,to the amplifier 308. The controller 216 may also provide a core enablesignal CE to the amplifier 308 to facilitate enabling or disabling theamplifier core 210 as further described herein. The controller 216 isalso shown receiving ACT and MODE for controlling the mode of operation.

Operation of the crystal amplifier 202 is now briefly described. Thecrystal amplifier 202 may initially be placed into a standby mode andremains in standby while ACT is negated. When MODE is set to OSC and thecrystal 702 is connected between XO and XI, ACT may be asserted toinitiate startup, in which case the controller 216 performs a startuproutine or process to initialize oscillation. The CE signal is assertedto enable the amplifier 308 as further described herein. C1EN and/orC2EN may be asserted (if negated), and CP1 and CP2 may be adjusted toset C1 and C2 to their tune values. The startup process is not furtherdescribed, but generally includes starting with a high value of corebias current via CBA until oscillation is achieved. Once oscillation isdetermined to be achieved, the controller 216 adjusts CBA to reduce thecore bias current to a steady state level.

In one embodiment, the steady state current level of the core biascurrent is known. For example, the controller 216 may store a digitalsteady state (SS) value in the memory 310 and adjust CBA to the SS valuefor steady state operation. The memory 310 may be a read-only memory(ROM) or the like. Alternatively, the memory 310 may be a random accessmemory (RAM) or the like for determining and storing one or moredifferent SS values during operation. In one embodiment, the controller216 may perform an automatic gain control (AGC) process or the like todetermine the steady state level of the core bias current that achievesa signal level at XI or XO, determines the corresponding SS value, andstores the SS value into the memory 310 for future use. When ACT is nextnegated low, the controller 216 may perform a shutdown operation or thelike to place the amplifier core 202 back into the standby mode.Alternatively, ACT may remain asserted or not be provided inconfigurations in which the crystal amplifier 202 remains enabled.

In the OSC mode of operation, the controller 216 may perform the AGCprocess upon each startup, such as for determining an adjusted SS valuefor each operating session, or in response to another stimulus or event,such as a temperature change or any other prompt from other circuitry onthe IC 100 or from the electronic system. In one embodiment, thecontroller 216 asserts SEL to select XI or XO and monitors the signallevel via LD provided by the level detector 304 while adjusting CBA.When the level is at a predetermined target level determined by aselected threshold value (e.g., a selected one of TH1, TH2, etc.,provided via L_TH), the level detector 304 asserts LD indicating thatthe signal level has reached the threshold, the controller 216determines the steady state level for the core bias current.

When MODE indicates the AMP mode of operation, then the amplifier core210 is instead used to amplify an external oscillating signal receivedvia XI to provide an amplified oscillation signal on XO as an output. CEis asserted to enable the amplifier 308. C1EN and C2EN may be negatedand CP1 and CP2 may be set to zero or the like to effectively disable orotherwise remove C1 and C2 from the circuit. Alternatively, C2 may beenabled and its capacitance adjusted to be used as part of a capacitivevoltage divider to reduce the amplitude of the external oscillationsignal. The controller 216 asserts CBA to cause the current source 306to provide the core bias current at a level suitable for the AMP mode.The value of CBA for the AMP mode may be predetermined and stored in thememory 310, shown as the AMP value. In the AMP mode, the core biascurrent may be set to a current level to set the corresponding amplitudeof the amplified oscillation signal on XO at a predetermined targetlevel. If the AMP value is not provided or otherwise needs to bedetermined, then the controller 216 may use the AGC process in a similarmanner, except that the controller 216 asserts SEL to select XO and thelevel detector 304 selects the appropriate threshold value for settingthe amplitude of XO at the target level by adjusting CBA. Oncedetermined, the value of CBA may be stored as the AMP value in thememory 310.

The ability to perform the AGC process to adjust the amplitude of theoscillation signal on XO is particularly advantageous for the AMP modeof operation. The core amplifier 210 may drive multiple devices in whicheach device may present a corresponding load. The AGC process selectingXO for amplitude adjustment may be performed once to adjust the corebias current for a given load level to set the amplitude of theoscillation signal on XO to the target level. If the load changes, or ifother operating conditions cause the amplitude on XO to vary, the AGCprocess may be run again to re-adjust the core bias current to set thesignal amplitude of XO back to the target level. Thus, the AGC processmay be performed one and/or may be repeated on a periodic basis. It isnoted that the AGC process may not be necessary for either of the OSC orAMP modes of operation. In a configuration in which the core biascurrent is known or predetermined, the core bias current is set by thecontroller 216 to the appropriate value during operation (such as, forexample, by retrieving a stored value in the memory 310).

When MODE indicates the BYP mode of operation, the controller 216 setsCBA to set the core bias current to zero, and negates CE to disable theamplifier 308. The capacitance of C2 may be set to zero, or may be setto a suitable value to control the amplitude of the external oscillatingsignal provided to the IC 100 via XI.

FIG. 4 is a schematic diagram of the amplifier 308 according to a CMOSconfiguration. In this case, the CMOS amplifier 308 includes a P-channeltransistor P1, an N-channel transistor N1, a decoupling capacitor CD, abias resistor RB, an enable switch S1, a first degeneration resistor R1,and a second degeneration resistor R2. CD is coupled between the sourcenode 307 and GND. R1 is coupled between the source node 307 and a sourceterminal of P1, and has a control input receiving R1A from thecontroller 216. The gate terminal of P1 is coupled to the amplifierinput node 206, and the drain terminal of P1 is coupled to the amplifieroutput node 204. N1 has its drain terminal coupled to the amplifieroutput node 204, its gate terminal coupled to the amplifier input node206, and its source terminal coupled to one terminal of R2. The otherterminal of R2 is coupled to GND, and R2 has a control input receivingR2A from the controller 216. RB and S1 are coupled in series between theamplifier input node 206 and the amplifier output node 204.

The CMOS amplifier 308 is enabled by asserting CE to close switch S1 anddriving the core bias current to a suitable current level depending uponthe mode of operation. The CMOS amplifier 308 is disabled by negating CEto open switch S1 and to set the core bias current to zero. Thedegeneration resistors R1 and R2 may be set by the controller 216 tosuitable values to reduce frequency drift in the OSC mode, or may be setto zero (or shorted) if desired. In the illustrated embodiment, theresistors R1 and R2 are shown as adjustable resistors. In an alternativeembodiment, at least one of the resistors R1 and R2 may be fixed. Inanother alternative embodiment, either one of the resistors R1 and R2may be eliminated (e.g., replaced by a short). Also, R1 and R2 may havethe same resistance, or may have different resistances.

It is noted that each of the transistors described herein, including P1and N1, are one of at least two different conductivity types, such aseither N-type (e.g., N-channel) or P-type (e.g., P-channel). Eachtransistor includes two current terminals (e.g., drain and sourceterminals), and a control terminal (e.g., gate terminal). In theillustrated configuration, each transistor may be configured as a MOStransistor or a FET or the like, including any one of variousconfigurations of MOSFETs and the like. For example, the N-typetransistors may be NMOS transistors or NFETs, and the P-type transistorsmay be PMOS transistors or PFETs.

FIG. 5 is a schematic diagram of amplifier 308 according to an NMOSconfiguration in which P1, CD, and R1 may be eliminated. The currentsource 306 is provided for both configurations. For the NMOS amplifier308, however, node 307 is effectively merged into node 204 since P1 andR1 are eliminated, and the current source 306 provides the core biascurrent directly to the amplifier output node 204. RB and S1 remaincoupled in series between nodes 204 and 206 in the same manner.Operation is substantially similar and only one degeneration resistor,shown as R2, is provided. R2 may be controlled in similar manner and/oreliminated or shorted.

FIG. 6 is a simplified schematic diagram of an adjustable tune capacitor600 that may be used as either one or both of the capacitors C1 and C2.The tune capacitor 500 includes a pair of capacitor terminals 602 and604 representing the terminals of the tune capacitor (C1 or C2) that itimplements. Generally, the capacitor terminal 604 is coupled to GND foreach tune capacitor, and the capacitor terminal 602 for C1 is coupled tothe amplifier output node 204 (XO) and the capacitor terminal 602 for C2is coupled to the amplifier input node 206 (XI).

The tune capacitor 600 includes a series of N+1 capacitors C0, C1, . . ., CN and a corresponding series of N+1 N-channel transistor switchesN0-NN, in which each capacitor is coupled in series with the currentterminals of a corresponding one of the transistor switches between thecapacitor terminals 602 and 604. Thus, C0 is coupled in series with N0between the terminals 602 and 604, C1 is coupled in series with N1between the terminals 602 and 604, and so on, each forming one ofmultiple switch-capacitor pairs coupled in parallel between thecapacitor terminals 602 and 604. One terminal of each of the capacitorsC0-CN is coupled to the capacitor terminal 602. In each case, the drainterminal of the transistor switch is coupled to the other terminal of acorresponding one of the capacitors, and the source terminal is coupledto the capacitor terminal 604. Each of the transistor switches N0-NN hasa gate terminal receiving a corresponding one of N+1 control bitsCPX<0>, CPX<1>, CPX<N> from the controller 216, in which “X” is either“1” or “2” for CP1 or CP2, respectively. Thus, CPX<0> is provided to thegate terminal of N0, CPX<1> is provided to the gate terminal of N1, andso on.

A series of N+1 resistors R are further provided, each having oneterminal coupled to the junction between the resistor-transistor switchpairs between the capacitor terminals 602 and 604. The other terminal ofeach resistor R is coupled to one current terminal of a correspondingone of a series of N+1 pass gates (a.k.a., transmission gates) G0, G1, .. . , GN. The other current terminal of each of the pass gates G0-GN iscoupled to a bias voltage VB. Each pass gate G0-GN is shown implementedas a parallel combination of a P-channel transistor and an N-channeltransistor, in which the source terminal of one of the transistors ofeach pass gate is coupled to the drain terminal of the other, andvice-versa. Each pass gate includes a P-gate control terminal (gateterminal of internal P-channel transistor) and an N-gate controlterminal (gate terminal of internal N-channel transistor). The P-gatecontrol terminal of each pass gate G0-GN receives a corresponding one ofthe control bits CPX<0>-CPX<N>. The corresponding N-gate controlterminal of each pass gate G0-GN receives a corresponding one ofinverted control bits CPX<0>_B-CPX<N>_B, in which CPX<0>_B is aninverted version of CPX<0>, CPX<1>_B is an inverted version of CPX<1>,and so on.

An additional “balance” capacitor CBX and transistor switch NEN may becoupled in series between the capacitor terminals 602 and 604, in whichCBX is CB1 for C1 and CB2 for C2. An enable signal CXEN is provided tothe gate terminal of NEN, in which CXEN is C1EN for C1 and C2EN for C2.An additional resistor R is coupled between the drain terminal of NENand to one current terminal of another pass gate GE. The other currentterminal the pass gate GE is coupled to a bias voltage VB. The P-gatecontrol terminal of the pass gate GE receives CXEN, and thecorresponding N-gate control terminal of the pass gate GE receives CXENB, which is an inverted version of CXEN.

Although not shown, there is an additional parasitic capacitance CPI(not shown) associated with XI and another parasitic capacitance CPO(not shown) associated with XO, in which the parasitic capacitances CPIand CPO may be different (and usually are). The balance capacitor CBX isintended to compensate for the difference in parasitic capacitances ofXI and XO, so that the addition of CBX (CB1 for C1 coupled to XO and/orCB2 for C2 coupled to XI) equalizes the capacitances applied to XI andXO before adjustment of C1 and C2. In one embodiment, CBX is only addedto one of the adjustable capacitors. For example, the parasiticcapacitance CPI on XI may be greater than the parasitic capacitance CPOon XO, so that CB1 is only added to the tune capacitor C1 while CB2 isomitted for C2 (or CB2=0), to equalize capacitance, or CPO+CB1=CPI. Inanother embodiment CBX is added to both adjustable capacitors withcorresponding capacitances to equalize capacitance of XI and XO beforeadjustment. In either case, a balance capacitor is added to either C1 orC2, or both, to compensate for the parasitic capacitance of XI and XO toan equalized capacitance CEQ, or CB1+CPO=CB2+CPI=CEQ.

In operation of the adjustable tune capacitor 600, each control bitCPX<0>-CPX<N> is asserted high to turn on the corresponding transistorswitch N0-NN to connect the corresponding capacitor C0-CN between thecapacitor terminals 602 and 604, and to turn off the corresponding passgate G0-GN. Each control bit CPX<0>-CPX<N> is negated low to turn offthe corresponding transistor switch N0-NN to remove or decouple thecorresponding capacitor C0-CN from the capacitor terminal 604 and toturn on the corresponding pass gate G0-GN to instead couple thecapacitor to VB. For example, when CPX<0> is asserted high, N0 is turnedon so that C0 is coupled between the capacitor terminals 602 and 604,while the corresponding pass switch G0 is turned off to isolate C0 fromVB. When CPX<0> is negated low, N0 is turned off so that C0 is isolatedfrom the capacitor terminal 604, while the corresponding pass switch G0is turned on to connect C0 to VB. Thus, the control bits CPX<0>-CPX<N>collectively form a digital control value CPX used to couple selectedones of the capacitors C0-CN in parallel in which the capacitances ofthe selected capacitors add to select the corresponding capacitance forthe tune capacitor C1 or C2. The non-selected ones of the capacitorsC0-CN are tied off to the bias voltage to remove and isolate them fromthe circuit.

The controller 216 enables the adjustable tune capacitor 600 byasserting CXEN high to turn on NEN to couple CBX into the circuit, andby asserting the control bits CPX<0>-CPX<N> to the desired digitalcontrol value CPX. The controller 216 disables the adjustable tunecapacitor 600, or effectively removes it from the circuit, by negatingCXEN low to remove CBX from the circuit, and by asserting the controlbits CPX<0>-CPX<N> to a zero value for CPX.

FIG. 7 is a simplified block diagram illustrating the IC 100 configuredto operate in the OSC mode including the crystal 702 externally coupledbetween XO and XI, in which the crystal 702 combined with the crystalamplifier 202 forms a crystal oscillator 700. The controller 216 assertsCE high to enable the amplifier 308, and asserts CBA to cause thecurrent source 306 to drive the core bias current to the appropriatelevel to establish and maintain oscillation. The controller 216 sets thetune capacitors C1 and C2 to tune capacitances C1T and C2T,respectively, which establish oscillation at the target frequency.Generally, the combined capacitance of the capacitors C1 and C2 shouldbe equal to a tune (or load) capacitance CL, in whichCL=C1T*C2T/(C1T+C2T). C1T and C2T may each have the same capacitance,such as both equal to CL*2. C1T and C2T, however, may be different solong as their combined capacitance is CL.

The oscillating signal appearing on XI in the OSC mode may be providedto at least one external device, although the XO system 102 may notsupport more than one external device.

FIG. 8 is a simplified block diagram illustrating the IC 100 configuredto operate in the BYP mode. An external oscillator 802 provides anoscillating signal to the XI input of the IC 100. The controller 216negates CE low to disable the amplifier 308 and sets CBA so that thecore bias current is zero. This effectively disables the amplifier core210. The tune capacitor C2 is set to zero; in particular, C2EN isnegated low to turn off NEN and C2=0. The oscillating signal from theexternal oscillator 802 is provided to the squaring buffer 218 forgenerating the CLK1-CLKM signals as previously described. It is notedthat the external oscillator 802 may be implemented as the IC 100 in OSCmode as shown in FIG. 7. The external oscillator 802 may also be atemperature compensated crystal oscillator (TCXO) or the like, whichasserts the oscillation signal at the target amplitude.

FIG. 9 is a simplified block diagram illustrating the IC 100 configuredto operate in the AMP mode. The external oscillator 802 provides theexternal oscillation signal to XI and C2 is set to zero similar to thatdescribed for FIG. 8. In this case, however, the controller asserts CEhigh to enable the amplifier 308 and provides CBA so that the currentsource 306 provides a suitable core bias current to operate theamplifier core 210. Although the amplifier core 210 is enabled insimilar manner as the OSC mode, it is not used for establishingoscillation using the external crystal 702, but instead is used toamplify or otherwise buffer the external oscillation signal to XO. C1may also be set to zero.

The AMP mode of operation is particularly useful for daisy chainconfigurations. The OSC mode provides a method of generating anoscillation signal, but not necessarily for sharing that oscillationsignal for more than one other device, such as one other IC configuredin the BYP mode as shown in FIG. 8. When the amplifier core 210 isconfigured for the AMP mode, it serves as a buffer for driving multipleICs as further described herein. It is noted that the “amplified”oscillation signal at the XO output of the IC 100 configured to operatein the AMP mode does not mean that the amplitude (e.g., voltage level)of the oscillation signal is greater; instead, the signal is amplifiedin the sense that the IC 100 provides a greater drive capacity to drivethe input of multiple external devices as further described herein.

FIG. 10 is a simplified block diagram of a daisy chained configuration1000 of a set of “N” ICs IC1, IC2, IC3, . . . , ICN according to oneembodiment of the present invention. The external oscillator 802provides an oscillation signal to the XI input of the first IC IC1,which is configured in the AMP mode having its XO pin providing anamplified oscillation signal. The amplified oscillation signal isprovided to the XI pin of the remaining ICs IC2, . . . , ICN configuredin the BYP mode. As previously described in relation to FIG. 8, theexternal oscillator 802 may be implemented as the IC 100 in OSC mode asshown in FIG. 7, or may be a TCXO, or any other suitable oscillator. Inthis case, IC1 uses the external oscillation signal for itself andprovides an amplified oscillation signal for use by each of theremaining ICs IC2-ICN.

FIG. 11 is a simplified block diagram of a daisy chained configuration1100 of a set of “N” ICs IC1, IC2, IC3, . . . , ICN according to anotherembodiment of the present invention. The external oscillator 802provides an oscillation signal to the XI input of the first IC IC1,which is configured in the AMP mode having its XO pin providing anamplified oscillation signal in a similar manner as in the chainedconfiguration 1000. In this case, however, each of the remaining ICsIC2, . . . , ICN are also configured in the AMP mode. Thus, theamplified signal from the XO pin of ICI is provided to the XI pin ofIC2, having its XO pin providing another amplified signal to the XI pinof IC3, and so on up to the last ICN receiving an amplified oscillationsignal via its XI pin. In this case, ICI may use the externaloscillation signal for itself and provides an amplified oscillationsignal to IC2, which may use the amplified oscillation signal from IC1,but which also generates another amplified oscillation signal for IC3,which may use the amplified oscillation signal from IC2 for itself andwhich further provides another amplifed oscillating signal at its XOoutput, and so up to ICN, which receives an amplified oscillation signalat its XI input. In this case, a string of ICs in the AMP mode mayinclude any number of ICs since each is only loaded by the next IC inthe chain.

FIG. 12 is a simplified block diagram of a daisy chained configuration1200 of a first set of “N” ICs ICI-ICN and a second set of “P” ICs ICM,IC(M+1), . . . , ICP according to another embodiment of the presentinvention. ICI-ICN in FIG. 12 are configured in substantially the samemanner as for the chained configuration 1000. ICM is configured in theAMP mode, and the remaining ICs IC(M+1), . . . , ICP, each configured inthe BYP mode. The amplified oscillation signal from ICI is also providedto the XI pin of ICM, and the XO pin of ICM provides another amplifiedoscillation signal to the XI pin of the remaining ICs IC(M+1)-ICP. Thechained configuration 1200 illustrates that combinations of chains maybe implemented. Similar to the chained configuration 1000, the ICsIC2-ICN are driven by IC1, which also drives the input of ICM. ICM, inturn, drives the remaining ICs IC(M+1)-ICP. In any configuration inwhich loading becomes an issue in any subchain, an IC in that chain maybe configured in the AMP mode and used to drive additional ICs. It isalso noted that ICI may drive additional ICs (not shown) configured inthe AMP mode (similar to ICM), in which each of the additional AMP modeICs may each drive one or more additional ICs (not shown) configured inthe BYP mode (i.e., the chain of P ICs may be duplicated as many timesas desired). Also, ICM and any one or more of the additional AMP modeICs may further drive additional ICs in the AMP or BYP modes.

FIG. 13 is a simplified block diagram of a daisy chained configuration1300 of a multiple sets of multiple ICs according to another embodimentof the present invention. The daisy chained configuration 1300 includesthe external oscillator 802 providing an oscillation signal to the XIinput of the first IC ICI configured in the AMP mode, which has its XOpin providing an amplified oscillation signal to a first set of Nadditional ICs IC2, . . . , ICN configured in the BYP mode in a similarmanner as the daisy chained configuration 1000. The oscillation signalfrom the external oscillator 802 is also provided to the XI input of theanother IC ICM configured in the AMP mode, in which ICM, in turn, drivesanother set of ICs IC(M+1)-ICP in a similar manner as the daisy chainedconfiguration 1200. The oscillation signal from the external oscillator802 may be provided to additional ICs configured in the AMP mode, eachdriving additional sets of ICs configured in the AMP or BYP modes.

FIG. 14 is a simplified block diagram illustrating a first IC IC0configured to operate in the OSC mode including the crystal 702externally coupled between XO and XI, which provides an oscillationsignal to the XI input pin of another IC ICI configured in the AMP mode.IC0 incorporates a crystal oscillator (702, FIG. 7) generating theoscillation signal, which may be used as the external oscillator 802 inany of the daisy chained configurations 1000, 1100, 1200, 1300, or thelike. In the event that the external oscillator 802 is configured as theIC 100 in OSC mode, or IC0, the ICs IC2-ICN and/or ICM-ICP in any of thedaisy chain configurations do not load the “master” IC IC0, but insteadare driven by IC1. The number(s) N and/or P is only limited by the drivecapacity of IC1. The external oscillator 802 may be according toalternative configurations, such as the TCXO or the like.

The present description has been presented to enable one of ordinaryskill in the art to make and use the present invention as providedwithin the context of particular applications and correspondingrequirements. The present invention is not intended, however, to belimited to the particular embodiments shown and described herein, but isto be accorded the widest scope consistent with the principles and novelfeatures herein disclosed. Many other versions and variations arepossible and contemplated. Those skilled in the art should appreciatethat they can readily use the disclosed conception and specificembodiments as a basis for designing or modifying other structures forproviding the same purposes of the present invention without departingfrom the spirit and scope of the invention.

The invention claimed is:
 1. A crystal driver integrated circuit,comprising: an amplifier core, comprising: a controllable current sourcehaving an output that provides a core bias current to a source node; andan amplifier coupled between said source node and a reference node,having an input coupled to an amplifier input node and having an outputcoupled to an amplifier output node; an input pin coupled to saidamplifier input node and an output pin coupled to said amplifier outputnode; and a controller that operates said amplifier core in any one of aplurality of operating modes based on a mode input, including anoscillator mode for driving an external crystal coupled between saidinput and output pins to generate an oscillation signal at a targetfrequency, including an amplifier mode that amplifies an externaloscillating signal provided to said input pin to provide an amplifiedoscillation signal on said output pin, and including a bypass mode inwhich said controller disables said amplifier core.
 2. The crystaldriver integrated circuit of claim 1, wherein said controller adjustssaid current source to provide said core bias current so that saidoscillation signal on said input pin has a first target amplitude duringsaid oscillator mode, and wherein said controller adjusts said currentsource to provide said core bias current so that said amplifiedoscillation signal on said output pin has a second target amplitudeduring said amplifier mode.
 3. The crystal driver integrated circuit ofclaim 2, wherein said first and second target amplitudes are equal. 4.The crystal driver integrated circuit of claim 1, wherein during saidamplifier mode, said controller disables a first tune capacitor coupledto said amplifier output node and disables a second tune capacitorcoupled to said amplifier input node.
 5. The crystal driver integratedcircuit of claim 1, wherein said controller disables a tune capacitorcoupled to said amplifier input node during said bypass mode.
 6. Thecrystal driver integrated circuit of claim 1, wherein said invertingamplifier comprises one of a PMOS amplifier and an NMOS amplifier. 7.The crystal driver integrated circuit of claim 1, further comprising: amemory that stores a first and second values; and wherein saidcontroller uses said first value to adjust said current source to setsaid core bias current during said oscillator mode, and uses said secondvalue to adjust said current source to set said core bias current duringsaid amplifier mode.
 8. The crystal driver integrated circuit of claim1, further comprising: a select circuit having an output that conveys aselected one of said amplifier input node and said amplifier output nodebased on a select input; a level detector having an input coupled tosaid output of said select circuit and having an output providing alevel value to said controller; and wherein said controller controlssaid select input of said select circuit to select said amplifier inputnode to set a level of said core bias current for said oscillator mode,and controls said select input of said select circuit to select saidamplifier output node to set a level of said core bias current for saidamplifier mode.
 9. A crystal driver daisy chain configuration,comprising: a plurality of crystal driver integrated circuits coupled ina daisy chain configuration, each comprising: an amplifier core,comprising: a controllable current source having an output that providesa core bias current to a source node; and an amplifier coupled betweensaid source node and a reference node, having an input coupled to anamplifier input node and having an output coupled to an amplifier outputnode; an input pin coupled to said amplifier input node and an outputpin coupled to said amplifier output node; and a controller thatoperates said amplifier core in any one of a plurality of operatingmodes based on a mode input, including an oscillator mode for driving anexternal crystal coupled between said input and output pins to generatean oscillation signal at a resonant frequency, and an amplifier modethat amplifies an external oscillating signal provided to said input pinto provide an amplified oscillation signal on said output pin; andwherein at least one of said plurality of crystal driver integratedcircuits is operated in said amplifier mode having an output pinproviding an amplified oscillation signal to an input pin of at leastone other one of said plurality of crystal driver integrated circuits.10. The crystal driver daisy chain configuration of claim 9, furthercomprising a crystal oscillator providing an oscillation signal to aninput pin of one of said plurality of crystal driver integrated circuitsoperated in said amplifier mode.
 11. The crystal driver daisy chainconfiguration of claim 10, wherein said crystal oscillator comprises afirst one of said plurality of crystal driver integrated circuitsoperated in said oscillator mode having an input pin providing saidoscillation signal.
 12. The crystal driver daisy chain configuration ofclaim 9, wherein: a first one of said plurality of crystal driverintegrated circuits is operated in said amplifier mode having an inputpin receiving an external oscillation signal and having an output pinproviding a first amplified oscillation signal; and wherein a second oneof said plurality of crystal driver integrated circuits is operated insaid amplifier mode having an input pin coupled to said output pin ofsaid first one and having an output pin providing a second amplifiedoscillation signal.
 13. The crystal driver daisy chain configuration ofclaim 9, wherein each of said plurality of crystal driver integratedcircuits are operated in said amplifier mode, including a first onehaving an input pin receiving an external oscillating signal and a lastone receiving an amplified oscillation signal.
 14. The crystal driverdaisy chain configuration of claim 9, wherein said plurality of modesincludes a bypass mode in which said controller disables an amplifiercore of a crystal driver integrated circuit operated in said bypassmode.
 15. The crystal driver daisy chain configuration of claim 14,wherein: a first one of said plurality of crystal driver integratedcircuits is operated in said amplifier mode having an input pinreceiving an external oscillation signal and having an output pinproviding an amplified oscillation signal; and wherein a second one ofsaid plurality of crystal driver integrated circuits is operated in saidbypass mode having an input pin coupled to said output pin of said firstone for receiving said amplified oscillation signal.
 16. The crystaldriver daisy chain configuration of claim 15, wherein said plurality ofcrystal driver integrated circuits includes at least one additionalcrystal driver integrated circuit operated in said bypass mode having aninput pin coupled to said output pin of said first one for receivingsaid amplified oscillation signal.
 17. The crystal driver daisy chainconfiguration of claim 14, wherein: a first one of said plurality ofcrystal driver integrated circuits is operated in said amplifier modehaving an input pin receiving an external oscillation signal and havingan output pin providing a first amplified oscillation signal; wherein asecond one of said plurality of crystal driver integrated circuits isoperated in said bypass mode having an input pin coupled to said outputpin of said first one for receiving said first amplified oscillationsignal; and wherein a third one of said plurality of crystal driverintegrated circuits is operated in said amplifier mode having an inputpin coupled to said output pin of said first one for receiving saidfirst amplified oscillation signal and having an output pin providing asecond amplified oscillation signal.
 18. The crystal driver daisy chainconfiguration of claim 17, wherein a fourth one of said plurality ofcrystal driver integrated circuits is operated in said bypass modehaving an input pin coupled to said output pin of said second one forreceiving said second amplified oscillation signal.
 19. The crystaldriver daisy chain configuration of claim 14, wherein: a first pluralityof said plurality of crystal driver integrated circuits are eachoperated in said amplifier mode having an input pin receiving anexternal oscillation signal and having an output pin providing acorresponding one of a plurality of amplified oscillation signals; and asecond plurality of said plurality of crystal driver integrated circuitsare each operated in said bypass mode, each having an input pin forreceiving one of said plurality of amplified oscillation signals.
 20. Acrystal driver integrated circuit, comprising: an amplifier core,comprising: a controllable current source having an output that providesa core bias current to a source node; and an amplifier coupled betweensaid source node and a reference node, having an input coupled to anamplifier input node and having an output coupled to an amplifier outputnode; an input pin coupled to said amplifier input node and an outputpin coupled to said amplifier output node; and a controller thatoperates said amplifier core in any one of a plurality of operatingmodes based on a mode input, including an oscillator mode for driving anexternal crystal coupled between said input and output pins to generatean oscillation signal at a target frequency, and including an amplifiermode in which said amplifier core is operative to amplify an externaloscillating signal provided to said input pin to increase a drivecapacity of an amplified oscillation signal provided on said output pin.